Henry Wong
Intel (Hillboro)
(Work performed while at the University of Toronto)

Although FPGAs continue to grow in capacity, FPGA-based soft processors have grown little because of the difficulty of achieving higher performance in exchange for area. Superscalar out-of-order processor microarchitectures have been used successfully for hard processors for many years, but have so far been avoided for FPGAs due to the area increase and the expectation that a loss in clock frequency would more than offset the instructions-per-cycle (IPC) gains.

This talk summarizes my attempt at designing an out-of-order x86 CPU for FPGA. With careful microarchitectural choices and circuit design, I show that it is possible to build a complex microarchitecture on an FPGA, getting about 2.7x performance per clock and 0.8x clock frequency of Altera's Nios II/f single-issue in-order processor. This talk will cover a high-level overview of the microarchitecture and some of the interesting LUT-based circuits used in the processor.

Documentation

To learn more, read Henry Wong's dissertation at http://hdl.handle.net/1807/80713 .

Slides

Slides for the talk in PDF format.

Video:

To access the live webcast of the talk (active at 16:28 of the day of the presentation) and the archived version of the talk, use the URL SU-EE380-20190605. This is a first class reference and can be transmitted by email, Twitter, etc.

A URL referencing a YouTube view of the lecture will be posted HERE a week or so following the presentation.

About the Speaker:

Henry Wong did his graduate studies at the University of British Columbia (M.A.Sc., 2008) and University of Toronto (Ph.D., 2017). He joined Intel (Hillsboro) in 2018 and currently works on CPU architecture. In his chronically-insufficient spare time, he maintains a website for teaching Verilog, a web-based CPU simulator, and occasionally reverse-engineers things using microbenchmarks.